View KB2516_4371825.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

triple 8-bit analog-to-digital converte r KB2516 (preliminary) 1 summary the KB2516 is a triple 8-bit analog-to-digital converter optimized for digitizing r/g/b graphics signal from pc and workstation. its 140msps encode rate capability and analog bandwidth of 500mhz supports support display resolution of up to sxga (1280 1024) class. the ic also includes a pll (phase locked loop) system that can be locked on horizontal line frequency, and generates the adc clock. features analog bandwidth of 500mhz 3 clamps for 256 programmable levels 3 programmable gain amplifiers analog input range: 0.5vpp to 1.0vpp triple 8-bit adc sampling rate up to 140mhz fully integrated pll to generate the adc clock, which can be locked to a hsync integrated pll divider programmable clock phase control ( f step = 7.5 ) integrated sog separator and hsync input polarity detector single and double pixel width output data bus support i 2 c and 3-wire serial interface power down mode 1.25w power dissipation ordering information device package ordering information KB2516 144-lqfp-2020 applications rgb high speed digitizing lcd desktop monitor plasma display pannel panel related products ks2530 frc & scaler
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 2 blcok diagram b_in g_in g_in blue channel green channel clamp red channel adc r_outb<7:0> g_outa<7:0> output drver clamp control gain control cka (from pll) output mode 8-bit 8-bit g_outa<7:0> g_outb<7:0> b_outa<7:0> b_outb<7:0> divider pfd vco phase shifter ckb cka cka i 2 c and 3-wire pll gain control clamp control pll control adc output mode control sync processor vsync out hsync out sda scl sen i 2 c_3w hsync in sog in vsync in
triple 8-bit analog-to-digital converter KB2516 (preliminary) 3 electrical characeristics symbol parameter conditions min. typ. max. unit power supply vddc_p pre-amp analog supply voltage for r, g, b channels 4.75 5.0 5.25 v vddc_a adc analog supply voltage for r, g, b channels 4.75 5.0 5.25 v vdda_a adc analog supply voltage for r, g, b channels 3.0 3.3 3.6 v vddd_a adc digital supply voltage for r, g, b channels 4.75 5.0 5.25 v vdd_a adc digital supply voltage for r, g, b channels 3.0 3.3 3.6 v vddr output driver supply voltage for r, g, b channels 3.0 3.3 3.6 v vdd_p pll supply voltage 3.0 3.3 3.6 v vdd_s interface logic supply voltage 3.0 3.3 3.6 v iddc_p pre-amp analog supply current 55 65 75 ma iddc_a adc analog supply current 5v supply - 66 - ma idda_a adc analog supply current 3.3v supply - 33 - ma iddd_a adc digital supply current 5v supply - 10 - ma idd_a adc digital supply current 3.3v supply - 20 - ma iddr output driver supply current fclk = 140mhz, ramp input ma idd_p pll supply current fclk = 100mhz - 76 - ma idd_s interface logic supply current - - ma ptot total power consumption fclk = 180mhz, ramp input - 1.25 - w pre-amp f-3db amplifier bandwidth for r, g, b channels - 500 - mhz vin rgb input voltage range 0.5 0.7 1.0 vpp vbs input bias voltage for r, g, b channels 1.7 1.9 2.1 v avmax voltage gain max 1.6 2.3 2.9 db d acg coarse gain diff. between ch. for r, g, b channels -1.0 0.0 1.0 db d af1 fine gain diff. 1 between ch. for r, g, b channels -1.0 0.0 1.0 db d af2 fine gain diff. 2 between ch. for r, g, b channels -1.0 0.0 1.0 db tr pre-amp rising time for r, g, b channels - 1 - ns tf pre-amp falling time for r, g, b channels - 1 - ns vbrt1 brightness voltage (1) for r, g, b channels - 1.5 - v vbrt2 brightness voltage (2) for r, g, b channels - 2.3 - v vbrt3 brightness voltage (3) for r, g, b channels - 3.0 - v notes: 1. coarse brt = 80, fine brt = 00 2. coarse brt = 80, fine brt = 80 3. coarse brt = 80, f ine brt = ff
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 4 symbol parameter conditions min. typ. max. unit sync processor sogdet1 sog sync detect level 1 0.1 - - v sogdet2 sog sync detect level 2 - - 1.0 v analog-to-digital converter vreft reference top voltage 1.7 1.8 1.9 v vrefb reference bottom voltage 1.2 1.3 1.4 v inl dc integral non-linearity fclk = 75mhz, ramp input -1.0 - 1.0 lsb dnl dc differential non-linearity fclk = 75mhz, ramp input -0.5 - 0.5 lsb sndr signal to noise & distortion ratio fclk = 100mhz 36 - - db maxrate max. conversion rate 170 - - mhz ct cross talk fclk = 100mhz - - -36 db trd digital output rising time - - 2 ns tfd digital output falling time - - 2 ns phase-locked loop fref pll reference clock frequency 20 - 150 khz fclk maximum clock frequency 180 mhz drpll pll divider ratio 512 - 4095 fvco vco output clock frequency 17 197 mhz tcap pll capture time in start-up condition - 4 - ms trcap pll re-capture time in lock condition - - 300 us f step phase shift step tamb = 25 c - 7.5 - deg j pll pll jitter fclk = 180mhz - 200 - ps
triple 8-bit analog-to-digital converter KB2516 (preliminary) 5 digital specifications characteristics symbol min typ max unit logic input high level input voltage vih vdd - 0.5 - - v low level input voltage vil - - vss + 0.5 v high level input current iih - 10 - ua low level input current iil - 10 - ua input capacitance cin - 5 - pf logic output high level output voltage voh vdd - 0.5 - - v low level output voltage vol - - vss + 0.5 v high level input current ioh - 100 - ua low level input current iol - 100 - ua
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 6 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vdda_ar vssa_ar r_in vddc_pr r_vout1 vssc_pr r_clpc vddc_ag vssc_ag vdda_ag vssa_ag g_in vddc_pg g_vout1 vssc_pg g_clpc vddc_ab vssc_ab vdda_ab vssa_ab vssa_ab vddc_pb b_vout1 vssc_pb b_clpc vddc_sp vssc_sp clpex detcap sog_in hsync_in hsmic sogout vdd_si vss_si i2c_3w r_outb0 r_outb1 r_outb2 r_outb3 r_outb4 r_outb5 r_outb6 r_outb7 vddr_ga vssr_ga g_outa0 g_outa1 g_outa2 g_outa3 g_outa4 g_outa5 g_outa6 g_outa7 g_outb0 g_outb1 g_outb2 g_outb3 g_outb4 g_outb5 g_outb6 g_outb7 vddr_gb vssr_gb b_outa0 b_outa1 b_outa2 b_outa3 b_outa4 b_outa5 b_outa6 b_outa7 addr_ex0 addr_ex1 sda scl sen coast adc_ckex vdd_pp vss_pp vdd_pv vctrl itest1 vdd_pc vss_pc vdd_po vss_po vdd_pd vss_pd vss_pk ckb vdd_pk ckc vbb1 vssr_bb vddr_bb b_outb7 b_outb7 b_outb6 b_outb5 b_outb4 b_outb3 b_outb2 b_outb1 b_outb0 vssr_ba vddr_ba vssc_ar vddc_ar itest vdd_dac vss_dac vbb2 vddd_a vssd_a vinp vinn vreft vrefb vddg vssg pdb resetb_ex hsynco adc_ckb adc_ck vsynco vdd_a vss_a nc2 nc1 vssr_ra vddr_ra r_outa0 r_outa1 r_outa2 r_outa3 r_outa4 r_outa5 r_outa6 r_outa7 vssr_rb vddr_rb KB2516 144-tqfp-2020
triple 8-bit analog-to-digital converter KB2516 (preliminary) 7 pin description table 1. pin description no name description 1 vssc_ar red channel adc 0v analog power supply 2 vddc_ar red channel adc 5v analog power supply 3 r_in red channel analog input signal 4 vddc_pr red channel pre-amp 5v power supply 5 r_vout1 red channel pre-amp output signal 6 vssc_pr red channel pre-amp 0v power supply 7 r_clpc red channel clamp control external cap. 8 vdda_ag green channel adc 3.3v analog power supply 9 vssa_ag green channel adc 0v analog power supply 10 vssc_ag green channel adc 0v analog power supply 11 vddc_ag green channel adc 5v analog power supply 12 g_in green channel analog input signal 13 vddc_pg green channel pre-amp 5v power supply 14 g_vout1 green channel pre-amp output signal 15 vssc_pg green channel pre-amp 0v power supply 16 g_clpc green channel clamp control external cap. 17 vdda_ab blue channel adc 3.3v analog power supply 18 vssa_ab blue channel adc 0v analog power supply 19 vssc_ab blue channel adc 0v analog power supply 20 vddc_ab blue channel adc 5v analog power supply 21 b_in blue channel analog input signal 22 vddc_pb blue channel pre-amp 5v power supply 23 b_vout1 blue channel pre-amp output signal 24 vssc_pb blue channel pre-amp 0v power supply 25 b_clpc blue channel clamp control external cap. 26 vddc_sp syncproc 5v power supply 27 vssc_sp syncproc 0v power supply 28 clpex external clamp signal input pin 29 detcap sog polarity output 30 sog_in sog signal input pin 31 hsync_in hsync signal input pin 32 test
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 8 table 1. pin description (continued) no name description 33 sogout sog output signal pin 34 vdd_si serial interface 3.3v digital power supply 35 vss_si serial interface 0v digital power supply 36 i2c_3w serial interface mode selection between i 2 c and 3-wire 37 addr_ex0 slave address control bit 38 addr_ex1 slave address control bit 39 sda serial interface data signal pin 40 scl serial interface clock signal pin 41 sen signal enable for 3-wire serial interface 42 coast coast signal input 43 adc_ckex external analog to digital converter clock input 44 vdd_pp pll 3.3v phase detector power supply 45 vss_pp pll 0v phase detector power supply 46 vss_pv pll 0v analog power supply 47 vdd_pv pll 3.3v analog power supply 48 vctrl vco control voltage 49 itest1 bandgap reference current test pin 50 vdd_pc pll 3.3v charge-pump power supply 51 vss_pc pll 0v charge-pump power supply 52 vdd_po pll 3.3v vco power supply 53 vss_po pll 0v vco power supply 54 vdd_pd pll 3.3v digital power supply 55 vss_pd pll 0v digital power supply 56 vss_pk pll 0v clock driver power supply 57 ckb pll output clock with adc frequency (phase control available) 58 vdd_pk pll 3.3v clock driver power supply 59 ckc pll output clock with adc frequency (phase control available) 60 vbb1 substrate 0v power supply 61 vssr_bb blue channel adc output b driver power supply (0v) 62 vddr_bb blue channel adc output b driver power supply (3.3v) 63 b_outb7 blue channel adc digital output b bit 7 64 b_outb6 blue channel adc digital output b bit 6 65 b_outb5 blue channel adc digital output b bit 5 66 b_outb4 blue channel adc digital output b bit 4 67 b_outb3 blue channel adc digital output b bit 3
triple 8-bit analog-to-digital converter KB2516 (preliminary) 9 table 1. pin description (continued) no name description 68 b_outb2 blue channel adc digital output b bit 2 69 b_outb1 blue channel adc digital output b bit 1 70 b_outb0 blue channel adc digital output b bit 0 71 vssr_ba blue channel adc output a driver power supply (0v) 72 vddr_ba blue channel adc output a driver power supply (3.3v) 73 b_outa7 blue channel adc digital output a bit 7 74 b_outa6 blue channel adc digital output a bit 6 75 b_outa5 blue channel adc digital output a bit 5 76 b_outa4 blue channel adc digital output a bit 4 77 b_outa3 blue channel adc digital output a bit 3 78 b_outa2 blue channel adc digital output a bit 2 79 b_outa1 blue channel adc digital output a bit 1 80 b_outa0 blue channel adc digital output a bit 0 81 vssr_gb green channel adc output b driver power supply (0v) 82 vddr_gb green channel adc output b driver power supply (3.3v) 83 g_outb7 green channel adc digital output b bit 7 84 g_outb6 green channel adc digital output b bit 6 85 g_outb5 green channel adc digital output b bit 5 86 g_outb4 green channel adc digital output b bit 4 87 g_outb3 green channel adc digital output b bit 3 88 g_outb2 green channel adc digital output b bit 2 89 g_outb1 green channel adc digital output b bit 1 90 g_outb0 green channel adc digital output b bit 0 91 g_outa7 green channel adc digital output a bit 7 92 g_outa6 green channel adc digital output a bit 6 93 g_outa5 green channel adc digital output a bit 5 94 g_outa4 green channel adc digital output a bit 4 95 g_outa3 green channel adc digital output a bit 3 96 g_outa2 green channel adc digital output a bit 2 97 g_outa1 green channel adc digital output a bit 1 98 g_outa0 green channel adc digital output a bit 0 99 vssr_ga green channel adc output a driver power supply (0v) 100 vddr_ga green channel adc output a driver power supply (3.3v) 101 r_outb7 red channel adc digital output b bit 7 102 r_outb6 red channel adc digital output b bit 6
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 10 table 1. pin description (continued) no name description 103 r_outb5 red channel adc digital output b bit 5 104 r_outb4 red channel adc digital output b bit 4 105 r_outb3 red channel adc digital output b bit 3 106 r_outb2 red channel adc digital output b bit 2 107 r_outb1 red channel adc digital output b bit 1 108 r_outb0 red channel adc digital output b bit 0 109 vddr_rb red channel adc output b driver power supply (3.3v) 110 vssr_rb red channel adc output b driver power supply (0v) 111 r_outa7 red channel adc digital output a bit 7 112 r_outa6 red channel adc digital output a bit 6 113 r_outa5 red channel adc digital output a bit 5 114 r_outa4 red channel adc digital output a bit 4 115 r_outa3 red channel adc digital output a bit 3 116 r_outa2 red channel adc digital output a bit 2 117 r_outa1 red channel adc digital output a bit 1 118 r_outa0 red channel adc digital output a bit 0 119 vddr_ra red channel adc output a driver power supply (3.3v) 120 vssr_ra red channel adc output a driver power supply (0v) 121 nc1 no connection 122 nc2 123 vss_a adc 0v digital power supply 124 vdd_a adc 3.3v digital power supply 125 vsynco vsync output 126 adc_ck adc clock output 127 adc_ckb inverted adc clock output 128 hsynco hsync output 129 resetb_ex external inverted reset signal input 130 pdb power down control pin (input) 131 vssg adc 0v analog power supply 132 vddg adc 3.3v analog power supply 133 vrefb adc reference bottom voltage 134 vreft adc reference top voltage 135 vinn adc negative input for test 136 vinp adc positive input for test 137 vssd_a adc 0v digital power supply
triple 8-bit analog-to-digital converter KB2516 (preliminary) 11 table 1. pin description (continued) no name description 138 vddd_a adc 5v digital power supply 139 vbb2 substrate 0v power supply 140 vss_dac pre-amp dac 0v analog power supply 141 vdd_dac pre-amp dac 5v analog power supply 142 itest pre-amp control dac current test pin 143 vdda_ar red channel adc 3.3v analog power supply 144 vssa_ar red channel adc 0v analog power supply
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 12 description of each block ad2516x is equipped with a pre-amp that can control the gain and clamp level and can generate the pixel clock synchronized to input hsync through the internal pll. it then converts the rgb signal from analog -to- digital by synchronizing to the generated clock. it has a maximum conversion speed of 180mhz and is capable of supporting up to uxga (1600 1200). dac amp1 gain control 8 bit vin cex clamp brightness control 8 bit gm1 gm2 dac amp2 vout1 vout (to adc) figure 1. pre-amp block diagram
triple 8-bit analog-to-digital converter KB2516 (preliminary) 13 figure 1 is a block diagram of the pre-amp that is used in ad2516x. a clamp circuit is required to set the input dc level because the rgb signal input is ac coupled as it passes through the capacitor to be sent to the pre- amp. the signal to control the clamp is made from the hsync signal in the sync processor block. the clamp level control, which uses an 8-bit dac, has two modes, first, the coarse level control that controls 3 rgb channels simultaneously and, second, the fine level control that controls each channel clamp level independently. the input signal is gain controlled through the 8-bit dac for a maximum gain amplification of 2.3db. as in the clamp level control, the pre-amp has two modes: 1.) coarse level control that controls 3 rgb channels simultaneously and 2.) fine level control which controls them independently. t/h 15 comps vref_tap gen. digital correction logic output driver ovf udf channel a<7:0> 8 channel b<7:0> 8 8 4 5 t/h vin 31 comps output mode control figure 2. adc block diagram figure 2 which has the 2-step pipeline configuration is a block diagram of the adc used in ad2516x. it uses 1 overlap bit for digital correction and supports 3 output modes, signal channel mode, dual channel interleaving mode, and dual channel parallel mode. the sync processor block converts the hsync or sog input to a positive hsync signal, which can be processed by pll, and also makes the clock signal needed for clamp level control from the hsync. when hsync and sog inputs enter simultaneously, it is designed to place priority on the hsync.
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 14 vco pfd divider synchro phase shifter mux mux mux 0/180 0/180 0/180 hsynch divck hsynch divck 12 bits from micom hsynco, vsynco ckc ckb clkadc figure 3. pll block diagram figure 3 is a block diagram of the pll used in ad2516x. it generates the pixel clock by using the positive hsync signal from the sync processor block and the divider coefficient determined by the resolution. the reference clock frequency range is between 20khz - 150khz and the maximum output clock frequency is 180mhz. it produces two clock signals having the adc clock frequency and each signal can have 7.5 phase control. ad2516x is controlled entirely through serial interface, which supports two modes -12c bus and 3-wire interface.
triple 8-bit analog-to-digital converter KB2516 (preliminary) 15 register configration pre-amp sub addr. bit name description default value 00h <7:0> s00<7:0> rgb coarse gain control 80h 01h <7:0> s01<7:0> r fine gain control 80h 02h <7:0> s02<7:0> g fine gain control 80h 03h <7:0> s03<7:0> b fine gain control 80h 04h <7:0> s04<7:0> rgb coarse bright control 80h 05h <7:0> s05<7:0> r fine bright control 80h 06h <7:0> s06<7:0> g fine bright control 80h 07h <7:0> s07<7:0> b fine bright control 80h 08h <4> phsync hsync (input) polarity 0 00h <3> hsel hsync select 0 <2> clpenb clamp control 0 <1:0> cw<1:0> clamp pulse width control 00 09h <7:0> dactest<7:0> dac output selection for test ffh analog to digital converter (adc) sub addr. bit name description default value 0ah <7:6> m<1:0> output mode selection 00 00h <5> adck_enb adc clock output enable 0 <4> adck_inv adc clock output inverting 0 <3> adck_sel adc clock selection control 0 <2:1> adom<1:0> adc output buffer control 00 <0> 0
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 16 phase locked loop (pll) sub addr. bit name description default value 0bh <7:6> ifrsh<1:0> vco free running control 00 24h <5:3> ifrsel<2:0> vco range control 100 <2:0> icpsel<2:0> charge pump current control 100 0ch <7> vsinv vsync out polarity 0 00h <6> deinv den out polarity 0 <5:0> ac<5:0> cka phase control 000000 0dh <7:6> hsynmod<1:0> hsync out polarity 00 00h <5:0> bc<5:0> ckb phase control 000000 0eh <6> pcoast coast (input) polarity 0 00h <5:0> cc<5:0> ckc phase control 000000 0fh <7:0> div<11:0> divider control msb <11:4> 01101000 68h 10h <7:4> divider control lsb <3:0> 0000 00h <1:0> test <9:0> test out length msb <9:8> 00 11h <7:0> test out length lsb <7:0> 00000000 00h 12h <7:0> test <7:0> test out delay 00000100 04h 13h <7:0> hsd<11:0> hsync out length msb <11:4> 00000000 00h 14h <7:4> hsync out length lsb <3:0> 0100 40h <3:0> vsl<11:0> vsync out length msb <11:8> 0000 15h <7:0> vsl vsync out length lsb <7:0> 00000011 03h 16h <7:0> vsd<7:0> vsync out delay 00000000 00h 17h <7> cka_enb cka output enable 0 00h <6> ckb_enb ckb output enable 0 <5> ckc_enb ckc output enable 0 <4> cka_inv cka (adc input clock) inverting 0 <3> ckb_inv ckb inverting 0 <2> ckc_inv ckc inverting 0 <1> vi_gain pll vi converter gain control 0
triple 8-bit analog-to-digital converter KB2516 (preliminary) 17 i 2 c and 3-wire serial interface block description interface pin: input: i 2 c_3w, sen, scl, addr_ex<1:0> in-out: sda pin description: i 2 c_3w: serial interface mode selection 0 ? i 2 c interface mode, 1 ? 3-wire interface mode sen: 3-wire interface mode data enable signal 0 ? enable, 1 ? disable sda: serial data input output port scl: serial interface reference clock input addr_ex<1:0>: i 2 c slave address identifier
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 18 i 2 c timing diagram from master to slave from slave to master - s : start condition - p : stop condition - rs: repeated start condition write mode: r/w = 0 s slave address ack sub address ack sub address ack p write mode: r/w = 0 auto r/w x x a4 a3 a2 a1 a0 auto: sub address auto increment control bit - 0: disable 1: enable auto = 0 s slave address ack 0xxxxxxx (sub-address) ack data ack 0 0xxxxxxx (sub-address) ack data ack p auto = 1 s slave address ack 1xxxxxxx (sub-address: n) ack data (sub-address: n) ack 0 data (sub-address: n+1) ack data (sub-address: n+2) ack p auto = 1 s slave address ack 1xxxxxxx (sub-address: n) ack data (sub-address: n) ack 0 data (sub-address: n+1) ack data (sub-address: n+2) ack p read mode: r/w = 1 (auto = x) s slave address ack sub address (n) ack data (sub-address: n) ack r/w data (sub-address: n+1) ack data (sub-address: n+2) ack p rs data (sub-address: n+3) ack
triple 8-bit analog-to-digital converter KB2516 (preliminary) 19 wired interface timing diagram auto sub address format write mode: r/w = 0 auto: sub address auto increment control bit - 0: disable 1: enable r/w a4 a3 a2 a1 a0 auto = 0: sen scl sda sub-address (n) data (n) sub-address (m) data (m) auto = 1: sub-address auto increment sen scl sda sub-address (n) data (n) data (n+1) data (n+2) figure 4. wired interface write mode timing diagram
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 20 read mode: r/w = 1 (auto = x) sen scl sda sub-address (n) data (n) data (n+1) data (n+2) from master to slave from slave to master figure 5. wired interface read mode timing diagram serial interface description pre-amp gain control coarse gain control (s00) rgb coarse gain control with same value. (dynamic gain range: 40db) fine gain control (s01 - s03) rgb fine gain control independently. (dynamic gain range : 11 db) coarse brightness control (s04) rgb coarse brightness control with same value. (clamp range: 0 - 4v) fine brightness control (s05 - s07) rgb fine bright control independently. (clamp range: -0.5v - 0.5v) sync processor control hsync sele ction control (hsel) hsel = 0: internally polarity converted hsync is used hsel = 1: default hsync is used hsync input polarity control (phsync) it is available if hsel = 1 phsync = 0: default hsync input is used phsync = 1: inverted hsync input is used clamp control clock selection (clpenb) clpenb = 0: internal clamp signal clpenb = 1: external clamp signal (by clpex)
triple 8-bit analog-to-digital converter KB2516 (preliminary) 21 clamp pulse width control (cw) cw<1:0> pulse width 00 0.31us 01 0.54us 10 0.78us 11 1.01us dactest output selection control (dactest) select one of eight dac output current dactest<7:0> selected dac 11111111 no selection 11111110 coarse gain control dac 11111101 red channel fine gain control dac 11111011 green channel fine gain control dac 11110111 blue channel fine gain control dac 11101111 coarse brightness control dac 11011111 red channel fine brightness control dac select 10111111 green channel fine brightness control dac select 01111111 blue channel fine brightness control dac select analog-to-digital converter (adc) control output mode selection (m) m<1:0> output mode 00 single channel output mode 01 dual channel interleaving output mode 10 dual channel parallel output mode
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 22 output mode adc_ck single channel output mode d0 d1 d2 d3 d4 d5 channel a channel b hz dual channel interleaving output mode d0 d2 d4 d1 d3 d5 channel a channel b dual channel parallel output mode d0 d2 d4 d1 d3 d5 channel a channel b adc clock output control (adck_enb) adck_enb = 0: output clock is enabled adck_enb = 1: output clock is disabled (hz) adc clock output inverting control (adck_inv) adck_inv = 0: default adc_ck and adc_ckb output adck_inv = 1: inverted adc_ck and adc_ckb output adc clock selection control (adck_sel) adck_sel = 0: internal pll output is used adck_sel = 1: external clock (adc_ckex) is used adc output buffer state control (adom) adom<1:0> output buffer state 00 normal output mode 01 01010101 10 10101010 11 high impedance phase-locked loop (pll) control vco free running frequency control (ifrsh) ifrsh<1:0> free running frequency 00 default vco max. freq. 01 increase vco max. freq. 7.5% 10 increase vco max. freq. 15% 11 increase vco max. freq. 30%
triple 8-bit analog-to-digital converter KB2516 (preliminary) 23 vco frequency range control (ifrsel) ifrsel<2:0> frequency range (mhz) ifrsel<2:0> frequency range (mhz) 000 17 - 53 100 103 - 143 001 34 - 78 101 136 - 165 010 65 - 103 110 162 - 187 011 94 - 118 111 181 - 197 charge pump current control (icpsel) icpsel<2:0> current ( ua) icpsel<2:0> current ( ua) 000 50 100 500 001 100 101 750 010 150 110 1400 011 350 111 vsynco polarity control (vsinv) vsinv = 0: non-inverted vsync output vsinv = 1: inverted vsync output deno polarity control (deinv) deinv = 0: non-inverted deno output deinv = 1: inverted deno output hsynco polarity control (hsynmod) hsynmod<1:0> output polarity 00 positive hsynco 01 negative hsynco 10 same polarity with input hsync 11 inverted polarity with input hsync coast input polarity control (pcoast) pcoast = 0: default coast signal is used pcoast = 1: inverted coast signal is used pll output clock phase control (ac, bc, cc) ac<5:0>: adc clock phase control bc<5:0>: ckb output clock phase control cc<5:0>: ckc output clock phase control 0 to 47 is available 7.5 phase control by lsb
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 24 ~ ~ ~ ~ t d1 t hs_delay t hs_length t d2 t hs ~ ~ t d4 t d3 t den_length t den_delay hsync adc_ck hsynco deno t hs : hsynco period t hs_delay : hsync input (hsync) to hsync output (hsynco) delay t hs_length : hsync output (hsynco) high duration t den_delay : hsynco rising edge to deno rising edge delay t den_length : data enable output (deno) high duration t d1 : adc_ck rising edge to hsynco rising edge delay t d2 : adc_ck rising edge to hsynco falling edge delay t d3 : adc_ck rising edge to deno rising edge delay t d4 : adc_ck rising edge to deno falling edge delay figure 6. hsynco and deno output timing diagram divider register (div) this register controls the pll frequency. default value is 1664 (680h) ths = t div (t: vco clock period, 512 div 4096) hsynco duty control (hsd) ths_length = hsd t - td1 + td2, hsd 3 5 deno signal delay control (ded) tden_delay = ded t - td1 + td3, ded 3 5 deno duty control (del) tden_length = (div - ded - del) t - td3 + td4, del 3 5
triple 8-bit analog-to-digital converter KB2516 (preliminary) 25 t d5 t vs_delay t vs_length t d6 coast hsynco vsynco t vs_delay : coast rising edge to vsynco rising edge delay t vs_length : vsynco signal length (high duration) t d5 : hsynco rising edge to vsynco rising edge delay t d6 : hsynco rising edge to vsynco falling edge delay ~ ~ ~ ~ fig7. vsynco output timing diagram vsynco signal delay control (vsd) tvs_delay = vsd div t - td5, vsd 3 0 vsynco signal length control (vsl) tvs_length = vsl div t - td5 + td6, vsl 3 1 pll output clo ck enable (cka_enb, ckb_enb, ckc_enb) 0: output is enabled 1: output is disabled (low output) pll output clock inverting control (cka_inv, ckb_inv, ckc_inv) 0: non-inverted clock output 1: inverted clock output pll vi converter gain control (vi_gain) 0: 375 ua/v 1: 470 ua/v
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 26 timing diagram cka (from pll) aq aqp 2.1ns qp qod (single ch.) qod (dual ch.) 0.23ns 0.5ns figure 9. adc clock timing diagram
triple 8-bit analog-to-digital converter KB2516 (preliminary) 27 adc main timing aq coarse tha coarse adc fine tha fine adc dcl out n n+1 n+2 n+3 n+4 n+5 n+6 n-1 n n+1 n+2 n+3 n+4 n+5 track track track track track track track hold hold hold hold hold hold hold track track track track track track hold hold hold hold hold hold hold track n-1 n n+1 n+2 n+3 n+4 n-4 n-3 n-2 n-1 n n+1 output driver timing single channel mode n-5 n-4 n-3 n-2 n-1 n n+1 douta qod n-5 n-3 n-1 n+1 n-6 n-4 n-2 n dual channel mode doutb douta interleaving mode qod n-6 n-4 n-2 n doutb douta parallel mode n-7 n-5 n-3 n-1 figure 10. adc timing diagram
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 28 application circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vdda_ar vssa_ar r_in vddc_pr r_vout1 vssc_pr r_clpc vddc_ag vssc_ag vdda_ag vssa_ag g_in vddc_pg g_vout1 vssc_pg g_clpc vddc_ab vssc_ab vdda_ab vssa_ab vssa_ab vddc_pb b_vout1 vssc_pb b_clpc vddc_sp vssc_sp clpex detcap sog_in hsync_in hsmic sogout vdd_si vss_si i2c_3w r_outb0 r_outb1 r_outb2 r_outb3 r_outb4 r_outb5 r_outb6 r_outb7 vddr_ga vssr_ga g_outa0 g_outa1 g_outa2 g_outa3 g_outa4 g_outa5 g_outa6 g_outa7 g_outb0 g_outb1 g_outb2 g_outb3 g_outb4 g_outb5 g_outb6 g_outb7 vddr_gb vssr_gb b_outa0 b_outa1 b_outa2 b_outa3 b_outa4 b_outa5 b_outa6 b_outa7 addr_ex0 addr_ex1 sda scl sen coast adc_ckex vdd_pp vss_pp vdd_pv vctrl itest1 vdd_pc vss_pc vdd_po vss_po vdd_pd vss_pd vss_pk ckb vdd_pk ckc vbb1 vssr_bb vddr_bb b_outb7 b_outb7 b_outb6 b_outb5 b_outb4 b_outb3 b_outb2 b_outb1 b_outb0 vssr_ba vddr_ba vssc_ar vddc_ar itest vdd_dac vss_dac vbb2 vddd_a vssd_a vinp vinn vreft vrefb vddg vssg pdb resetb_ex hsynco adc_ckb adc_ck vsynco vdd_a vss_a nc nc vssr_ra vddr_ra r_outa0 r_outa1 r_outa2 r_outa3 r_outa4 r_outa5 r_outa6 r_outa7 vssr_rb vddr_rb KB2516 144-tqfp-2020 75 w or 5 w 75 w or 5 w 75 w or 5 w 0.1uf 0.1uf 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 5k w vcc 0.1uf 0.1uf 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w 4.7k w vdda vdda 33 w 33 w 33 w 33 w 33 w 33 w 33 w 33 w c1 r1 c2 0.1uf
triple 8-bit analog-to-digital converter KB2516 (preliminary) 29 all supply pins have to be decoupled, with two capacitors: one for high frequencies (approximately 1nf) and one for the low frequencies (approximately 100nf or higher). pll loop filter (c1, c2, r1) f k i c c n n o p = + 1 2 1 2 p ( ) where : f n = the natural pll frequency k o = the vco gain n = the division number c 1 and c 2 = capacitors of the pll filter f r c f f z n z = = 1 2 1 2 1 1 p x and where : f z = loop filter zero frequency r 1 = the choosen resistance for the filter x = the damping factor c1, c2, and r1 values are selected to satisfy the following conditions. f f n ref @ 0 05 . x @ 1 5 .
KB2516 (preliminary) triple 8-bit analo g-to-digital converter 30 package dimension 144-lqfp-2020 #144 20.00 bsc 22.00 bsc 20.00 bsc 22.00 bsc 0.08 max 0.09-0.20 0-7 #1 0.50 bsc (1.25) 0.60 0.15 0.05-0.15 1.40 0.05 1.60 max 0.08 max 0.17-0.27

▲Up To Search▲

Price & Availability of KB2516

	To Download KB2516 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .